1. Field of the Invention
The present invention relates to a gain amplifier having a switched-capacitor structure for minimizing settling time, and more particularly, to a gain amplifier having a switched-capacitor structure capable of resetting its output terminal in advance to an estimated output voltage value rather than 0 when sampling an input signal, to reduce slewing time, so that settling time can be minimized.
The present invention is derived from a project entitled “Elements and Module for Ubiquitous Terminal [2006-S-006-02]” conducted as an IT R&D program for the Ministry of Information and Communication/Institute for Information and Technology Advancement (Republic of Korea).
2. Discussion of Related Art
Recent developments in image sensor technology have led to the embedding of digital cameras in mobile phones. Such image processing systems require a circuit that has low power consumption and is compact in size to enhance portability, among other functions.
In particular, an Analog Front-End (AFE) that processes a low-intensity analog signal output from a sensor uses a two-stage gain amplifier having the switched-capacitor (SC) structure illustrated in FIG. 1 to amplify a signal and to reduce noise.
FIG. 1 illustrates a conventional gain amplifier 100 having a switched-capacitor structure. The gain amplifier includes a two-stage amplifier 110 including two amplifiers, i.e., first and second amplifiers 111 and 112, a first switch SW1, to which an input signal VIN is applied from an input terminal, second and third switches SW2 and SW3, to which a common mode voltage VCM is applied, a sampling capacitor CS storing the input voltage at a first clock Q1, a miller capacitor CM for compensating for a frequency of the two-stage amplifier 110, a feedback capacitor CF connected between an input and an output of the two-stage amplifier 110, a parasitic capacitor CP connected between the first and second amplifiers 111 and 112 and ground, and a load capacitor CL connected between an output terminal of the two-stage amplifier 110 and ground.
Describing operations of the gain amplifier 100 according to phases of non-overlapping clocks Q1 and Q2, first, an analog input signal is stored in the sampling capacitor CS at the first clock Q1, an output voltage VOUT is reset to 0, the second switch SW2 connected to the common mode voltage VCM at the second clock Q2 is turned on, and the charge stored in the sampling capacitor CS is transferred to the feedback capacitor CF to determine an output voltage VOUT. Here, an output terminal of the amplifier is driven from 0, and a signal is amplified as much as a gain by CS/CF values to be output.
That is, the conventional gain amplifier 100 having the switched-capacitor structure stores the input signal in the sampling capacitor CS at the first clock Q1 using the non-overlapping clocks Q1 and Q2, and then amplifies the signal at the second clock Q2 based on a ratio of the sampling capacitor CS to the feedback capacitor CF.
However, in the conventional gain amplifier having the above switched-capacitor structure, since the output terminal of the amplifier is always reset to 0 during the first clock Q1 sampling the input signal, the output signal of the amplifier is always driven from 0 to be settled to a desired value during the second clock Q2. This causes slewing time in an amplification mode to be increased, so that overall settling time and power consumption are increased.